9th International Conference on Robotic, Vision, Signal by Haidi Ibrahim, Shahid Iqbal, Soo Siang Teoh, Mohd Tafir

By Haidi Ibrahim, Shahid Iqbal, Soo Siang Teoh, Mohd Tafir Mustaffa

The continuing is a set of study papers offered, on the ninth foreign convention on Robotics, imaginative and prescient, sign Processing & strength purposes (ROVISP 2016), by means of researchers, scientists, engineers, academicians in addition to commercial pros from everywhere in the globe to give their learn effects and improvement actions for oral or poster displays. the subjects of curiosity are as follows yet are usually not restricted to:

• Robotics, regulate, Mechatronics and Automation
• imaginative and prescient, picture, and sign Processing
• synthetic Intelligence and laptop Applications
• digital layout and functions
• Telecommunication structures and Applications
• strength approach and business Applications
• Engineering schooling

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Extra resources for 9th International Conference on Robotic, Vision, Signal Processing and Power Applications: Empowering Research and Innovation

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Mustaffa Fig. 2 Comparator with DTTS technique sub-threshold leakage is reduced. This is because sub-threshold leakage is considered as major contribution of static power in circuit. 38 × 10−23 J/K), n = Technology parameter, W/L = width/length, VTH = threshold voltage, VDS = drain-source voltage, VGS = gate-source voltage, VT = thermal voltage During active state, transistors PM4, PM5, NM5 and NM6 are ‘ON’ and ‘OFF’ in idle state. During idle state, there is no current flowing through the circuit.

The highest throughput achieved by the Table 2 Architectural characteristics of the proposed AES and Blowfish designs Algorithm Slices Slice LUTs LUT FF pairs IOBs AES 5200/301440 (1 %) 3667/19031 (19 %) 555/600 (92 %) Blowfish 2348/301440 (0 %) 17498/150720 (11 %) 2582/150720 (1 %) 1393/3537 (39 %) 3/600 (0 %) 24 R. Ahmad and W. Ismail Fig. 3 Performance comparison of the proposed AES and Blowfish with previous research works proposed architecture indicates that the said architecture has the highest encryption speed and the best performance.

The transistor is designed as high threshold voltage by increasing the body effect. Based on Eq. 1, by increasing the VSB, the source bulk voltage, the threshold voltage of the transistor can be increased. VTH = VTO + γ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffi jVSB + 2∅F j − j2∅F j ð1Þ where VTH = threshold voltage, VSB = source-to-body substrate bias 2∅F = is the surface Fermi potential, VTO = threshold voltage for zero substrate bias The leakage current can be reduced by using high VTH transistors during idle mode.

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